One stop electronic component supply Original FM38F16SAD-9MFD 4G bits DDR3(L) SDRAM DATA SHEET IC CHIP FBGA96

Product Specifications

• Density: 4G bits

• Organization

— 128M word x4 bits x 8 banks

— 64M word x8 bits x 8banks

— 32M word x16 bits x 8 banks

• Package

— 78-ball FBGA(X4/X8)

— 96-ball FBGA(X16)

— Lead-free (RoHS compliant) and Halogen-free

• Power supply: 1.35V (typ) of 1600

— VDD = 1.283V to 1.45V

— Backward compatible for VDD, VDDQ= 1.5V ± 0.075V

• Power supply: 1.5V ± 0.075V (typ) of 1866

• Data rate

— 1600Mbps/1333 Mbps (1.35V)

— 1866 Mbps (1.5V)

• 1KB page size

— Row address: A0 to A15(X4/X8)

— Column address: A0 to A9,A11(X4)

Product Features

• Double-data-rate architecture: two data transfers per clock cycle

• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver

• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

— Synchronous ODT

— Dynamic ODT

• 2KB page size A0 to A9(X8)

— Row address: A0 to A14(X16)

— Column address: A0 to A9(X16)

• Eight internal banks for concurrent operation

• Burst length (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

— Sequential (8, 4 with BC)

— Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11,13(1866)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11(1600/1333)

• /CAS Write Latency (CWL): 5, 6, 7, 8,9(1866)

• /CAS Write Latency (CWL): 5, 6, 7, 8(1600/1333)

• Precharge: auto precharge option for each burst access

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

— Average refresh period 

7.8μs at 0°C ≤ TC ≤+85°C 

3.9μs at +85°C < TC ≤+95°C

• Operating case temperature range

— TC = 0°C to +95°C

— Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern 

read out

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset function

• SRT range:

— Normal/extended

• Programmable Output driver impedance control

  Specifications

Actual product photos

Product Data Book：

For more product information, please download the PDF

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

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