Product Introduction

The high performance ispMACH 4000 family offers a SuperFAST CPLD solution. The family is a blend of two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families,the  ispMACH  4000  architecture  focuses  on  significant  innovations  to combine  the  highest  performance  with  low power in a flexible CPLD family.

The  ispMACH  4000  combines  high  speed  and  low  power  with  the  flexibility  needed  for  ease  of  design.  With  its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration.

The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packagesranging  from  44  to  256  pins/balls.  Table  1  shows  the  macrocell,  package  and  I/O  options,  along  with  other  keyparameters.

Products Features

■High Performance

•fMAX = 400MHz maximum operating frequency

•tPD = 2.5ns propagation delay

•  Up to four global clock pins with programmable clock polarity control

•  Up to 80 PTs per output

■Ease of Design

•  Enhanced macrocells with individual clock, reset, preset and clock enable controls

•  Up to four global OE controls

•  Individual local OE control per I/O pin

•  Excellent First-Time-FitTM and refit

•  Fast path, SpeedLockingTM Path, and wide-PT path

•  Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders

■Zero Power (ispMACH 4000Z) and Low Power (ispMACH 4000V/B/C)

•  Typical static current 10μA (4032Z)

•  Typical static current 1.3mA (4000C)

•  1.8V core low dynamic power

•  ispMACH 4000Z operational down to 1.6V VCC

Specifications

Payment&Transportation

Official Certificate&Certificate

Multiple product supply

Company office environment

Warehouse Real Shot

Standard packaging

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