XPC850SRZT80BU PowerQUICC™ Integrated Communications Processor Hardware Specifications

Product Descriptions

The MPC850 is a versatile, one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications, excelling particularly in communications and networking products. The MPC850, which includes support for Ethernet, is specifically designed for cost-sensitive, remote-access, and telecommunications applications. It is provides functions similar to the MPC860, with system enhancements such as universal serial bus (USB) support and a larger (8-Kbyte) dual-port RAM.

In addition to a high-performance embedded MPC8xx core, the MPC850 integrates system functions, such as a versatile memory controller and a communications processor module (CPM) that incorporates a specialized, independent RISC communications processor (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded MPC8xx core.

The CPM of the MPC850 supports up to seven serial channels, as follows: 

• One or two serial communications controllers (SCCs). The SCCs support Ethernet,  ATM (MPC850SR and MPC850DSL), HDLC and a number of other protocols,  along with a transparent mode of operation. 

• One USB channel 

• Two serial management controllers (SMCs) 

• One I2C port 

• One serial peripheral interface (SPI).

Product Features

The following list summarizes the main features of the MPC850: 

• Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC  architecture) with thirty-two 32-bit general-purpose registers (GPRs)  

— Performs branch folding and branch prediction with conditional prefetch, but  without conditional execution

— 2-Kbyte instruction cache and 1-Kbyte data cache (Harvard architecture) 

– Caches are two-way, set-associative  

– Physically addressed 

– Cache blocks can be updated with a 4-word line burst 

– Least-recently used (LRU) replacement algorithm 

– Lockable one-line granularity 

— Memory management units (MMUs) with 8-entry translation lookaside buffers  (TLBs) and fully-associative instruction and data TLBs 

— MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512  Kbytes, and 8 Mbytes; 16 virtual address spaces and eight protection groups 

• Advanced on-chip emulation debug mode 

• Data bus dynamic bus sizing for 8, 16, and 32-bit buses 

— Supports traditional 68000 big-endian, traditional x86 little-endian and modified  little-endian memory systems 

— Twenty-six external address lines 

• Completely static design (0–80 MHz operation)

• System integration unit (SIU) 

— Hardware bus monitor 

— Spurious interrupt monitor 

— Software watchdog 

— Periodic interrupt timer 

— Low-power stop mode 

— Clock synthesizer 

— Decrementer, time base, and real-time clock (RTC) from the PowerPC  architecture  

— Reset controller

— IEEE 1149.1 test access port (JTAG) 

• Memory controller (eight banks) 

— Glueless interface to DRAM single in-line memory modules (SIMMs),  synchronous DRAM (SDRAM), static random-access memory (SRAM),  electrically programmable read-only memory (EPROM), flash EPROM, etc. 

— Memory controller programmable to support most size and speed memory  interfaces 

— Boot chip-select available at reset (options for 8, 16, or 32-bit memory) 

— Variable block sizes, 32 Kbytes to 256 Mbytes

— Selectable write protection 

— On-chip bus arbiter supports one external bus master 

​— Special features for burst mode support

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