Hot sale original electronics Intel EPM7064LI84-15 IC CPLD 64MC 15NS 84PLCC Embedded

Product Details

General Description

The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. 

Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, 

ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.

Features...

■ High-performance, EEPROM-based programmable logic devices

   (PLDs) based on second-generation MAX® architecture

■ 5.0-V in-system programmability (ISP) through the built-in

   IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in

   MAX 7000S devices

   – ISP circuitry compatible with IEEE Std. 1532

■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

   devices

■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S

   devices with 128 or more macrocells

■ Complete EPLD family with logic densities ranging from 600 to

   5,000 usable gates (see Tables 1 and 2)

■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter

   frequencies (including interconnect)

■ PCI-compliant devices available

■ Open-drain output option in MAX 7000S devices

■ Programmable macrocell flipflops with individual clear, preset,

   clock, and clock enable controls

■ Programmable power-saving mode for a reduction of over 50% in

   each macrocell

■ Configurable expander product-term distribution, allowing up to

   32 product terms per macrocell

■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic

   pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat

   pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages

■ Programmable security bit for protection of proprietary designs

■ 3.3-V or 5.0-V operation

   – MultiVoltTM I/O interface operation, allowing devices to

      interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is

      not available in 44-pin packages)

   – Pin compatible with low-voltage MAX 7000A and MAX 7000B

      devices

■ Enhanced features available in MAX 7000E and MAX 7000S devices

   – Six pin- or logic-driven output enable signals

   – Two global clock signals with optional inversion

   – Enhanced interconnect resources for improved routability

   – Fast input setup times provided by a dedicated path from I/O

      pin to macrocell registers

   – Programmable output slew-rate control

■ Software design support and automatic place-and-route provided by

   Altera’s development system for Windows-based PCs and Sun

   SPARCstation, and HP 9000 Series 700/800 workstations

■ Additional design entry and simulation support provided by EDIF

   2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),

   Verilog HDL, VHDL, and other interfaces to popular EDA tools from

   manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,

   OrCAD, Synopsys, and VeriBest

■ Programming support

   – Altera’s Master Programming Unit (MPU) and programming

      hardware from third-party manufacturers program all

      MAX 7000 devices

   – The BitBlasterTM serial download cable, ByteBlasterMVTM

      parallel port download cable, and MasterBlasterTM

      serial/universal serial bus (USB) download cable program MAX

      7000S devices

Product Description

   Actual image of the product                

  Product Attributes

Product datasheet

For more information, please download

​

Payment&Transportation

Official Certificate&Certificate

Standard packaging

Multiple product supply

Welcome to visit our company

Warehouse Real Shot