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Hot sale Original KS8995MAI Telecommunication Circuits LAN Switching Circuit CMOS PQFP128 PLASTIC QFP-128
Manufacturer
Manufacturer Product Number
KS8995MAI
Description
KS8995MAI Telecommunication Circuits LAN Switching Circuit CMOS PQFP128 PLASTIC QFP-128
Package Condition
tray
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Product Details
| Description The KS8995MA/FQ is a highly-integrated Layer 2 managed switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems with both copper and optic fiber media. It also provides an extensive feature set such as tag/port based VLAN, quality of service (QoS) priority, management, MIB counters, dual MII interfaces and CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KS8995MA/FQ contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KS8995MA/FQ contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. Features • Integrated switch with five MACs and five fast Ethernet transceivers fully-compliant to IEEE 802.3u standard • Shared memory based switch fabric with fully non blocking configuration • 1.4Gbps high-performance memory bandwidth • 10BASE-T, 100BASE-TX, and 100BASE-FX modes • Dual MII configuration: MII-Switch (MAC or PHY mode MII) and MII-P5 (PHY mode MII). • IEEE 802.1q tag-based VLAN (16 VLANs, full-range VID) for DMZ port, WAN/LAN separation or inter VLAN switch links • VLAN ID tag/untag options, per-port basis • Programmable rate limiting 0Mbps to 100Mbps, ingress and egress port, rate options for high and low priority, per-port basis in 32Kbps increments • Flow control or drop packet rate limiting (ingress port) • Integrated MIB counters for fully-compliant statistics gathering, 34 MIB counters per port • Enable/Disable option for huge frame size up to 1916 bytes per frame • IGMP v1/v2 snooping for multicast packet filtering • Special tagging mode to send CPU info on ingress packet’s port value • SPI slave (complete) and MDIO (MII PHY only) serial management interface for control of register configuration • MAC-id based security lock option • Control registers configurable on-the-fly (port priority, 802.1p/d/q, AN...) • CPU read access to MAC forwarding table entries • 802.1d spanning tree protocol • Port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or MII • Broadcast storm protection with % control – global and per-port basis • Optimization for fiber-to-copper media conversion • Full-chip hardware power-down support (register configuration not saved) • Per-port based software power-save on PHY (idle link detection, register configuration preserved) • QoS/CoS packets prioritization supports: − Per port, 802.1p and DiffServ based • 802.1p/q tag insertion or removal on a per-port basis (egress) • MDC and MDI/O interface support to access the MII PHY control registers (not all control registers) • MII local loopback support • On-chip 64Kbyte memory for frame buffering (not shared with 1K unicast address table) • Wire-speed reception and transmission • Integrated look-up engine with dedicated 1K MAC addresses • Full duplex IEEE 802.3x and half-duplex back pressure flow control • Comprehensive LED support • 7-wire SNI support for legacy MAC interface • Automatic MDI/MDI-X crossover for plug-and-play • Disable automatic MDI/MDI-X option • Low power: − Core: 1.8V − Digital I/O: 3.3V − Analog I/O: 3.3V • 0.18µm CMOS technology • Temperature ranges: − Commercial: 0°C to +70°C − Industrial: –40°C to +85°C • Available in 128-pin PQFP package Applications • Broadband gateway/firewall/VPN • Integrated DSL or cable modem multi-port router • Wireless LAN access point plus gateway • Home networking expansion • Standalone 10/100 switch • Hotel/campus/MxU gateway • Enterprise VoIP gateway/phone • FTTx customer premise equipment • Managed media converter |
Product Description
| Type# | Description |
| ANSC PART# | ANSC- KS8995MAI |
| Package Description | Fqfp, Qfp128,.67x.93,20 |
| Length | 20 Mm |
| Moisture Sensitivity Level | 3 |
| Number of Functions | 1 |
| Number of Terminals | 128 |
| Operating Temperature-Max | 85 °C |
| Operating Temperature-Min | -40 °C |
| Package Body Material | Plastic/Epoxy |
| Package Code | FQFP |
| Package Equivalence Code | QFP128,.67X.93,20 |
| Package Shape | Rectangular |
| Package Style | Flatpack, Fine Pitch |
| Peak Reflow Temperature (Cel) | 240 |
| Qualification Status | Not Qualified |
| Seated Height-Max | 3.4 Mm |
| Supply Voltage-Nom | 1.8 V |
| Surface Mount | Yes |
| Technology | Cmos |
| Telecom IC Type | Lan Switching Circuit |
| Temperature Grade | Industrial |
| Terminal Finish | Tin/Lead (Sn85pb15) |
| Terminal Form | Gull Wing |
| Terminal Pitch | 0.5 Mm |
| Terminal Position | Quad |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Width | 14 Mm |
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KS8995MAI Telecommunication Circuits LAN Switching Circuit CMOS PQFP128 PLASTIC QFP-128
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