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Exact specifications should be obtained from the product data sheet.
Product Descriptions
■ High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at 25 MHz
■ On-Chip Floating Point Unit
— Supports IEEE 754 Floating Point Standard
— Full Transcendental Support
— Four 80-Bit Registers
— 13.6 Million Whetstones/s (Single Precision) at 25 MHz
■ 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached Instructions
■ Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored On-Chip (Sixteen 32-Bit Registers per Set)
— Register Scoreboarding
■ On-Chip Memory Management Unit
— 4 Gbyte Virtual Address Space per Task
— 4 Kbyte Pages with Supervisor/User Protection
■ Built-in Interrupt Controller
— 32 Priority Levels
— 248 Vectors
— Supports M8259A
— 3.4 µs Latency @ 25 MHz
■ Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
■ Multitasking and Multiprocessor Support
— Automatic Task dispatching
— Prioritized Task Queues
■ Advanced Package Technology
— 132-Lead Ceramic Pin Grid Array
Actual product photos
Product Data Manual:
For more product information, please download the PDF
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