MC68MH360CAI25L CPU32+ Microprocessor IC M683xx 1 Core, 32-Bit 25MHz 240-FQFP

Product Features

• MC68MH360-specific features 

— Up to 32 independent communication channels

— Arbitrary mapping of any of 0–31 channels to any of 0–31 TDM time slot 

— Can support arbitrary mapping of any of 0–31 channels to any of 0–63 TDM time slots in case of common Rx and Tx mapping 

— Up to three additional HDLC 64-Kbps channels at 25-MHz system clock 

— Simultaneous Ethernet support at 33-MHz system clock 

— Up to 64 DMA channels with linear buffer array 

• MPC860MH/DH-specific features 

— Up to 64 independent communication channels 

— Arbitrary mapping of any of 0–63 channels to any of 0–63 TDM time slots 

— Supports arbitrary mapping of any of 0–63 channels to any of 0–127 TDM time slots in case of common Rx and Tx mapping 

— Two simultaneous 32-channel E1 links at 50-MHz system clock 

— Up to 128 DMA channels with linear buffer array 

• Common features — Independent mapping for receive/transmit 

— Supports either transparent or HDLC protocols for each channel 

— Interrupt circular buffer with programmable size and overflow identification 

— Global loop mode — Individual channel loop mode through the SI 

— Programmable frame length (via SI) 

• Serial interface 

— Serial-multiplexed (full duplex) input/output 2048-, 1544-, or 1536-Kbps PCM highways 

— Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN basic rate, ISDN primary rate and user-defined 

— Subchanneling on each time slot 

— Allows independent transmit and receive routing, frame syncs, and clocking 

— Concatenation of any, not necessarily consecutive, time slots to channels independently for receive/transmit 

— Supports H0, H11, and H12 ISDN channels 

— Allows dynamic allocation of channels

• System interface

— On-chip bus arbitration for serial DMAs with no performance penalty 

— Efficient bus usage (no bus usage for nonactive channels and active channels that have nothing to transmit) 

— Efficient control of the interrupts to the CPU 

— Supports external buffer descriptors table 

— Uses on-chip enlarged dual-ported RAM for parameter storage

Product Specifications

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