Original packaging RM5271-250S Superscalar Microprocessor IC with External Cache Interface

Product Descriptions

The QED RM5271 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV  Instruction Set Architecture (ISA). It has a high-performance 64-bit integer unit, a high-throughput, fully pipelined  64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB,  a 32 KByte 2-way set associative instruction cache, a 32  KByte 2-way set associative data cache, and a high-performance 64-bit system interface with support for an optional  external secondary cache. 

The RM5271 can issue both an  integer and a floating point instruction in the same cycle. The RM5271 is ideally suited for high-end embedded control applications such as internetworking, high-performance  image manipulation, high-speed printing, and 3-D visualization.The RM5271 is also applicable to the low end workstation market where its balanced integer and floating-point  performance and direct support for a large secondary  cache (up to 2MB) provide outstanding price/performance.

Product Features

• Dual Issue superscalar microprocessor 

— 200, 225, 250, 266, 300, 350 MHz operating frequencies 

— 420 Dhrystone 2.1 MIPS maximum 

— SPECInt95 7.3, SPECfp95 8.3 maximum 

• High-performance system interface 

— 64-bitmultiplexed system address/data bus for optimum  price/performance with up to 125MHz operation frequency 

— High-performance write protocols to maximize uncached  write bandwidth 

— Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 

— IEEE 1149.1 JTAG boundary scan • Integrated on-chip caches 

— 32KB instruction and 32KB data - 2-way set associative 

— Virtually indexed, physically tagged

— Write-back and write-through on per page basis 

— Pipeline restart on first double for data cache misses 

• Integrated secondary cache controller (R5000 compatible) 

— Supports 512K or 2MByte block write-through secondary 

• Integrated memory management unit 

— Fully associative joint TLB (shared by I and D translations) 

— 48 dual entries map 96 pages 

— Variable page size (4KB to 16MB in 4x increments)

• High-performance floating point unit - up to 700 MFLOPS 

— Single cycle repeat rate for common single precision operations and some double precision operations

— Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations 

— Single cycle repeat rate for single precision combined multiply-add operation 

• MIPS IV instruction set 

— Floating point multiply-add instruction increases performance in signal processing and graphics applications 

— Conditional moves to reduce branch frequency 

— Index address modes (register + register) 

• Embedded application enhancements 

— Specialized DSP integer Multiply-Accumulate instruction and  3 operand multiply instruction 

— I and D cache locking by set 

— Optional dedicated exception vector for interrupts 

• Fully static CMOS design with power down logic 

— Standby reduced power mode with WAIT instruction 

— 3.5 Watts typical power @ 200MHz 

— 2.5V core with 3.3V IO’s 

• 304-pin SBGA package (31x31mm)

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