Hot-selling and scarce CY7C109B-15ZC SRAM - Asynchronous Memory IC 1Mbit Parallel 15 ns 32-TSOP spot stock

Product Descriptions

The CY7C109B/CY7C1009B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable One (CE1) and Write Enable (WE) inputs LOW and Chip Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip Enable One (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).

CY7C109B is available in standard 400-mil-wide SOJ and 32- pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package. The CY7C109B and CY7C1009B are functionally equivalent in all other respects.

Product Features

• High speed

— tAA = 12 ns

• Low active power

— 495 mW (max.)

• Low CMOS standby power

— 11 mW (max.) (L Version)

• 2.0V Data Retention

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE1, CE2, and OE options

• CY7C109B is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The CY7C1009B is available in a 300-mil-wide SOJ package

Product Specification

Product Photos

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