Hot-selling and scarce H5TQ2G63BFR-PBC DDR DRAM Memory IC FBGA-96 spot stock

Product Descriptions

The H5TQ2G83BFR and H5TQ2G63BFR are  2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density andhigh bandwidth . SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both risingand falling edges of the clock .While all addresses and control inputs are latched on the rising edges of theCK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both risingand falling edges of it . The data paths are internally pipelined and 8-bit prefetched to achieve very highbandwidth .

Product Features

•  VDD=VDDQ=1.5V +/- 0.075V

•   Fully differential clock inputs (CK, CK) operation

•   Differential Data Strobe (DQS, DQS)

•  On chip DLL align DQ, DQS and DQS transition with CK transition

•   DM masks write data-in at the both rising and falling edges of the data strobe

•  All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

•   Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported

•   Programmable additive latency 0, CL-1, and CL-2 supported

•  Programmable CAS Write latency (CWL) = 5, 6, 7,8,9,10

•   Programmable burst length 4/8 with both nibble sequential and interleave mode

•   BL switch on the fly

•   8banks

• AverageRefreshCycle (Tcaseof0 oC~95 oC)

-7.8 µs at 0oC ~85 oC

- 3.9 µs at 85oC ~ 95 oC

Commercial Temperature (0  oC~ 85 oC)

Industrial Temperature ( -40oC~ 85 oC)

•  Auto Self Refresh supported

•   JEDEC standard 82ball FBGA(x8), 96ball FBGA (x16)

•   Driver strength selected by EMRS

•   Dynamic On Die Termination supported

•  Asynchronous RESET pin supported

•   ZQ calibration supported

•   TDQS (Termination Data Strobe) supported (x8 only)

•   Write Levelization supported

•   8 bit pre-fetch

Product Photos

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