Hot-selling and scarce CY7C1051DV33-10ZSXIT SRAM - Asynchronous Memory IC 8Mbit Parallel 10 ns 44-TSOP spot stock

Product Descriptions

The CY7C1051DV33 is a high performance CMOS Static RAMorganized as 512 K words by 16-bits .  

To write to the device,take Chip Enable (CE)and Write Enable(WE)inputs LOW .If Byte LOW Enable (BLE)is LOW,then datafrom I/O pins (I/O 0–I/O 7),is written into the location specified onthe address pins (A 0–A 18).If Byte HIGH Enable (BHE)is LOW,then data from I/O pins (I/O 8–I/O 15)is written into the locationspecified on the address pins (A 0–A 18).    

To read from the device,take Chip Enable (CE)and OutputEnable (OE)LOW while forcing the Write Enable (WE)HIGH .IfByte LOW Enable (BLE)is LOW,then data from the memorylocation specified by the address pins appears on I/O 0–I/O 7 .IfByte HIGH Enable (BHE)is LOW,then data from memoryappears on I/O 8 to I/O 15.

The input/output pins (I/O 0–I/O 15) are placed  in ahigh-impedance state when the device is deselected (C E HIGH),the outputs are disabled (OE HIGH),the BHE and BLE aredisabled (BHE ,BLE HIGH),or a write operation (CE LOW,andWE LOW)is in progress .

The CY7C1051DV33 is available in a 44-pin TSOP II packagewith center power and ground (revolutionary)pinout and a48-ball FBGA package .

Product Features

■ Temperature ranges

❐ –40 °C to 85 °C

■ High speed

❐ tAA =10 ns

■ Low active power

❐ I CC =110 mA at f =100 MHz

■ Low CMOS standby power

❐ I SB2 =20 mA

■ 2.0-V data retention

■ Automatic power-down when deselected

■ Transistor-transistor logic (TTL)-compatible inputs and outputs

■ Easy memory expansion with CE and OE features

■ Available in Pb-free 48-ball fine ball grid array (FBGA)and 44-pin thin small outline package (TSOP)II packages

Product Specifications

Product Photos

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