Hot-selling and scarce CY7C1520KV18-250BZC SRAM - Synchronous, DDR II Memory IC 72Mbit Parallel 250 MHz 165-FBGA spot stock

Product Descriptions

The CY7C1518KV18, and CY7C1520KV18 are 1.8 Vsynchronous pipelined SRAM equipped with DDR II architecture .The DDR II consists of an SRAM core with advancedsynchronous peripheral circuitry and a 1-bit burst counter.Addresses for read and write are latched on alternate risingedges of the input (K)clock .Write data is registered on the risingedges of both K and K .Read data is driven on the rising edgesof C and C if provided,or on the rising edge of K and K if C/C arenot provided .On CY7C1518KV18 and CY7C1520KV18,theburst counter takes in the least significant bit of the externaladdress and bursts two 18-bit words in the case ofCY7C1518KV18 and two 36-bit words in the case ofCY7C1520KV18 sequentially into or out of the device .

Asynchronous inputs include an output impedance matchinginput (ZQ).Synchronous data outputs (Q,sharing the samephysical pins as the data inputs D)are tightly matched to the twooutput echo clocks CQ/CQ ,eliminating the need for separatelycapturing data from each individual DDR SRAM in the systemdesign .Output data clocks (C/C)enable maximum systemclocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled bythe K or K input clocks .All data outputs pass through outputregisters controlled by the C or C (or K or K in a single clockdomain) input clocks . Writes are conducted with on-chipsynchronous self-timed write circuitry.

Product Features

■ 72-Mbit density (4M ×18,2M ×36)

■ 333 MHz clock for high bandwidth

■ Two-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces (data transferred at 666 MHz)at 333 MHz

■ Two input clocks (K and K)for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C)to minimize clock skew and flight time mismatches

■ Echo clocks (CQ and CQ)simplify data capture in high speed systems

■ Synchronous internally self-timed writes

■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH

■ Operates similar to DDR-I device with 1 cycle read latency when DOFF is asserted LOW

■ 1.8 V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4 V–V DD)

❐ Supports both 1.5 V and 1.8 V IO supply

■ Available in 165-ball fine pitch ball grid array (FBGA)package (13 ×15 ×1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible Test Access Port

■ Phase-locked loop (PLL)for accurate data placement

Product Specifications

Product Photos

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