One-Stop Supply Electronic components Bom List PFC460 SOP-16 MCU Development Burn Controller

   Product Introduction

The PFC460 family is an ADC-Type of PADAUK’s parallel processing with touch function, fully static, MTP-based CMOS 8 bit*2 processor array that can execute four peripheral functions in parallel. It employs RISC architecture based on patent pending FPPA™ (Field Programmable Processor Array) technology and all the instructions are executed in one cycle except that some instructions are two cycles that handle indirect memory access.

4KW MTP program memory and 512 bytes data SRAM are inside for PFC460.

One up to 28 channels (including GND) 12-bit ADC is built inside the chip with one channel for internal Bandgap reference voltage or 0.25*VDD.

C-Touch hardware circuit is built inside the PFC460, which up to 24 IO pins could be selected as touch keys.

PFC460 provides a hardware 16-bit timer, two hardware 8-bit timers with PWM generation (Timer2, Timer3), three hardware 11-bit timers with PWM generation (PWMG0/1/2) and one new triple 11-bit timer with SuLED PWM generation (LPWMG0/1/2).

PFC460 also supports a PFG frequency modulation circuit, an Operational Amplifier (OPA) and a hardware comparator, plus one VDD/2 bias voltage generator for LCD display application and one 8x8 hardware multiplier to enhance hardware capability in arithmetic function.

   Product Features

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1.1. Special Features

 High EFT series

Especially fit for the products that are AC powered with even using RC step-down circuit, or require strong

noise immunity, or required high EFT capability (±4KV) for passing safety regulation tests.

 Operating temperature range: -40°C ~ 105°C

 ESD > 8 KV

1.2. System Features

 4KW MTP program memory for four FPPA units (programming cycle at least 1,000 times)

 512 Bytes data SRAM for four FPPA units

 One hardware 16-bit timer

 Two hardware 8-bit timers with PWM generation (Timer2/Timer3), Timer2/Timer3 also configured with NILRC oscillator. Its frequency is slower than ILRC and suitable for a more power-saving wake-up clock.

 Timer2/Timer3 PWM resolution is 6/7/8 bit

 Three hardware 11-bit PWM generators (PWMG0/PWMG1/PWMG2)

 One set triple 11bit SuLED (Super LED) PWM generators and timers(LPWMG0/LPWMG1/LPWMG2)

 Provide one PFG hardware circuit for precise frequency output

 Provide one hardware comparator

 Provide one OP Amplifier (OPA)

 Provide 1T 8x8 hardware multiplier

 26 IO pins with optional pull-high / pull-low resistor

 Every IO pin can be configured to enable wake-up function

 For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast

 Up to 24 IO pins could be selected as touch keys

 Built-in LDO hardware circuit provides 2V voltage reference for touch function

 Bandgap circuit to provide 1.20V reference voltage

 Up to 28-channel 12-bit resolution ADC with one channel comes from internal Bandgap reference voltage or 0.25*VDD

 Provide ADC reference high voltage: external input, internal VDD, Bandgap(1.20V), 4V, 3V, 2V

 Clock sources: internal high RC oscillator (IHRC), internal low RC oscillator (ILRC) and external crystal oscillator (EOSC)

 Provide four IO output capabilities to satisfy different application requirements

(1) PB0 drive current could option 0/10mA, and it sink current could option 108/20mA

(2) PB2~PB7 drive current could option 28/10mA, and it sink current could option 75/20mA

(3) PA0~PA4 drive/sink current =10mA/20mA

(4) PA5~PA7, PB1, PC0~PC7, PD0~PD1 drive/sink current =10mA/14mA

 Built-in VDD/2 bias voltage generator to provide 5COM×21SEG dots LCD display

 14 selectable levels of LVR reset from 2.0V to 4.5V

 8 selectable external interrupt pins

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