Products Features

• Modified Harvard architecture 

• C compiler optimized instruction set architecture 

• Flexible addressing modes 

• 83 base instructions 

• 24-bit wide instructions, 16-bit wide data path 

• Up to 144 Kbytes on-chip Flash program space 

• Up to 48K instruction words 

• Up to 8 Kbytes of on-chip data RAM 

• Up to 4 Kbytes of nonvolatile data EEPROM 

• 16 x 16-bit working register array 

• Up to 30 MIPS operation: 

- DC to 40 MHz external clock input 

- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x) 

• Up to 41 interrupt sources: 

- Eight user-selectable priority levels 

- Five external interrupt sources 

- Four processor traps

DSP Features

• Dual data fetch 

• Modulo and Bit-Reversed modes 

• Two 40-bit wide accumulators with optional saturation logic 

• 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier 

• All DSP instructions are single cycle: 

- Multiply-Accumulate (MAC) operation

 • Single-cycle ±16 shift

Peripheral Features

• High-current sink/source I/O pins: 25 mA/25 mA

• Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules

• 16-bit Capture input functions

• 16-bit Compare/PWM output functions:

• Data Converter Interface (DCI) supports common audio Codec protocols, including I2S and AC’97

• 3-wire SPI modules (supports four Frame modes)

• I2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing

• Two addressable UART modules with FIFO buffers

• Two CAN bus modules compliant with CAN 2.0B standard

Specifications

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Multiple product supply

Company office environment

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