Hot-selling and scarce LCMXO2-7000HC-5FG484ICA1 Field Programmable Gate Array (FPGA) IC BBGA spot stock

Product Descriptions

The MachXO2™ family of ultra low power, instant-on,  non-volatile PLDs has six devices with densities ranging  from 256 to 6864 Look-Up Tables (LUTs). In addition to  LUT-based, low-cost programmable logic these devices  feature Embedded Block RAM (EBR), Distributed RAM,  User Flash Memory (UFM), Phase Locked Loops (PLLs),  preengineered source synchronous I/O support,  advanced configuration support including dual-boot  capability and hardened versions of commonly used  functions such as SPI controller, I2C controller and  timer/counter. These features allow these devices to  be used in low cost, high volume consumer and system  applications.

The MachXO2 devices are designed on a 65 nm nonvolatile low power process. The device architecture  has several features such as programmable low swing  differential I/O and the ability to turn off I/O banks, onchip PLLs and oscillators dynamically. These features  help manage static and dynamic power consumption  resulting in low static power for all members of the  family.​

Product Features

1.1.1. Flexible Logic Architecture

 Six devices with 256 to 6864 LUT4s and 18 to 334 I/O

1.1.2. Ultra Low Power Devices

 Advanced 65 nm low power process

 As low as 22 μW standby power

 Programmable low swing differential I/O

 Stand-by mode and other power saving options

1.1.3. Embedded and Distributed Memory

 Up to 240 kbits sysMEM™ Embedded Block RAM

 Up to 54 kbits Distributed RAM

 Dedicated FIFO control logic

1.1.4. On-Chip User Flash Memory

 Up to 256 kbits of User Flash Memory

 100,000 write cycles

 Accessible through WISHBONE, SPI, I2C and JTAG interfaces

 Can be used as soft processor PROM or as Flash memory

1.1.5. Pre-Engineered Source Synchronous I/O

 DDR registers in I/O cells

 Dedicated gearing logic

 7:1 Gearing for Display I/O

 Generic DDR, DDRX2, DDRX4

 Dedicated DDR/DDR2/LPDDR memory with DQS support

1.1.6. High Performance, Flexible I/O Buffer

 Programmable sysI/O™ buffer supports wide range of interfaces:

 LVCMOS 3.3/2.5/1.8/1.5/1.2

 LVTTL

 PCI

 LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL

 SSTL 25/18

 HSTL 18

 MIPI D-PHY Emulated

 Schmitt trigger inputs, up to 0.5 V hysteresis

 I/O support hot socketing

 On-chip differential termination

 Programmable pull-up or pull-down mode

Product Photos

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