Hot-selling and scarce MT48LC4M16A2P-75:G SDRAM Memory IC 64Mbit Parallel 133 MHz 5.4 ns 54-TSOP II spot stock

Product Descriptions

The 64Mb SDRAM is a high-speed CMOS,dynamic     random -access     memory     containing67,108,864 bits .  It is internally configured  as  a quadbank DRAM with a synchronous interface  (all signalsare registered on the positive edge of the clock signal,CLK).  Each  of the  x4’s  16,777,216-bit  banks  is  organized as 4,096 rows by 1,024 columns by 4 bits . Each ofthe x8’s 16,777,216-bit banks is organized as 4,096 rowsby 512 columns by 8 bits . Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by16 bits .

Read  and  write  accesses  to  the  SDRAM  are  burstoriented; accesses start at a selected location and continue for a programmed number of locations in a programmed    sequence .    Accesses    begin    with    theregistration of an ACTIVE command, which is then followed by a READ or WRITE command . The address bitsregistered  coincident with  the  ACTIVE  command  areused to select the bank and row to be accessed  (BA0,BA1  select the bank; A0-A11  select the  row). The  ad -​dress bits registered coincident with the READ or WRITEcommand are used to select the starting column location for the burst access .

Product Features

•   PC66-,  PC100-,  and  PC133-compliant

•   Fully synchronous; all signals registered on positive edge of system clock

•   Internal pipelined operation;  column address can be changed every clock cycle

•   Internal banks for hiding row access/precharge

•   Programmable burst lengths:  1, 2, 4, 8, or full page

•   Auto  Precharge,  includes  CONCURRENT  AUTO PRECHARGE,  and Auto  Refresh Modes

•   Self Refresh Modes: standard and low power

•   64ms,  4,096-cycle  refresh

•   LVTTL-compatible  inputs  and  outputs

•   Single +3.3V ±0.3V power supply

Product Specification

Product Photos

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