You can contact me for the best price electronic components BOM matching list ic chip SOP8 PGS134

   Product Introduction

The PGS134 family is an MTP-based CMOS 8-bit microcontroller with 12bit ADC. It employs RISC architecture and all the instructions are executed in one cycle except that some instructions are two cycles that handle indirect memory access.

4KW MTP program memory, 512 bytes EEPROM and 256 bytes data SRAM are inside. One up to 14 channels 12-bit ADC is built inside the chip with multiple reference voltage sources selectable. PGS134 also provides six hardware timers: one is 16-bit timer, two are 8-bit timers with PWM generation, and three hardware 11-bit timers with PWM generation are also included. PGS134 also supports one hardware comparator and VDD/2 LCD bias voltage generator for LCD display application.

   Product Features

1.1. Special Features

 General purpose series

 Not supposed to use in AC RC step-down powered or high EFT requirement applications.

PADAUK assumes no liability if such kind of applications can not pass the safety regulation tests.

 Operating temperature range: -40°C ~ 85°C

1.2. System Features

 4K words MTP

 512 bytes EEPROM

 256 bytes SRAM(128 * 16 configuration)

 One hardware 16-bit timer

 Two hardware 8-bit timers with PWM generation

 Three hardware 11-bit PWM generators (PWMG0, PWMG1 & PWMG2)

 One hardware comparator

 Bandgap circuit to provide 1.20V reference voltage

 Up to 14-channel 12-bit resolution ADC with one channel comes from internal Bandgap reference voltage or 0.25*VDD

 ADC reference high voltage: external input, internal VDD, Bandgap 1.2V、1.6V、2.0V、2.4V、3.0V and 4.0V

 One 1T 8x8 hardware multiplier

 Max. 22 IO pins with optional pull-high and pull-low resistor

 Two different IO Driving capability group to meet different application requirements

(1) PB4, PB7 Drive/ Sink Current= 30mA/35mA (Strong) and 13mA/17mA (Normal)

(2) Other IOs (except PA5) Drive/ Sink Current = 11mA/(13 or 20) mA

 Every IO pin can be configured to enable wake-up function

 Built-in VDD/2 LCD bias voltage generator to provide maximum 4x17 dots LCD display

 Clock sources: IHRC, ILRC and EOSC (XTAL)

 For every wake-up enabled IO, two optional wake-up speed are supported: normal and fast

 Eight levels of LVR reset: 4.0V, 3.5V, 3.0V, 2.7V, 2.5V, 2.2V, 2.0V, 1.8V

 Two selectable external interrupt pins by code option

1.3. CPU Features

 8bit high performance RISC CPU

 98 powerful instructions

 Most instructions are 1T execution cycle

 Programmable stack pointer to provide adjustable stack level

 Direct and indirect addressing modes for data access. Data memories are available for use as an index pointer of Indirect addressing mode

 IO space and memory space are independent

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