Hot-selling and scarce H5TQ2G63BFR-11C 2Gb DDR3 SDRAM BGA spot stock

Product Features

•  VDD=VDDQ=1.5V +/- 0.075V

•   Fully differential clock inputs (CK, CK) operation

•   Differential Data Strobe (DQS, DQS)

•   On chip DLL align DQ, DQS and DQS transition with CK transition

•   DM masks write data-in at the both rising and falling edges of the data strobe

•  All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

•   Programmable CAS latency 6, 7, 8, 9, 10, 11 , 12, 13 and 14  supported

•   Programmable additive latency 0, CL-1, and CL-2 supported

•   Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9

•   Programmable burst length 4/8 with both nibble sequential and interleave mode

•   BL switch on the fly

•   8banks

• Average RefreshCycle (Tcaseof0 oC~95 oC)

-7.8 µs at 0oC ~85 oC

- 3.9 µs at 85oC ~ 95 oC

•  Auto Self Refresh supported

•   JEDEC standard 96ball FBGA(x16)

•   Driver strength selected by EMRS

•   Dynamic On Die Termination supported

•  Asynchronous RESET pin supported

•   ZQ calibration supported

•   Write Levelization supported

•   On Die Thermal Sensor supported

•   8 bit pre-fetch

Product Photos

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WhenCE is HIGH (deselected),the device assumes a standby mode at which the power dissipation can be reduced down to250 µW (typical) with CMOS input levels.