CDCVF2509APW 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE TSSOP24 spot stock

Product Descriptions

The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver . It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal . It is specifically designed for use with synchronous  DRAMs . The CDCVF2509A operates at a 3.3-V V_CC .  It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads .

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK . Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK . Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs . When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state . The deviceautomically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state .

Product Features

•     Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev . 1.1

•     Spread Spectrum Clock Compatible

•     Operating Frequency 20 MHz to 175 MHz

•     Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps

•     Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps

•     Advanced Deep Submicron ProcessResults in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices

•     Auto Frequency Detection to Disable Device (Power-Down Mode)

•     Available in Plastic 24-Pin TSSOP

•     Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

•     Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs

•     Separate Output Enable for Each Output Bank

•     External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input

•     25-Ω On-Chip Series Damping Resistors

•     No External RC Network Required

•     Operates at 3.3 V

Product Applications

•     DRAM Applications

•     PLL Based Clock Distributors

•     Non-PLL Clock Buffer

Product Specification

Product Photos

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