Hot-selling and scarce AD9510BCPZ Clock Fanout Buffer Divider IC LFCSP-6 spot stock

Product Descriptions

The AD9510 provides a multi-output clock distributionfunction along with an on-chip PLL core . The design emphasizeslow jitter and phase noise to maximize data converterperformance. Other applications with demanding phase noiseand jitter requirements also benefit from this part .

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The PLL section consists of a programmable reference divider(R); a low noise phase frequency detector (PFD); a precisioncharge pump (CP); and a programmable feedback divider (N).By connecting an external VCXO or VCO to the CLK2/CLK2Bpins, frequencies up to 1.6 GHz may be synchronized to theinput reference .

There are eight independent clock outputs . Four outputs areLVPECL (1 .2 GHz), and four are selectable as either LVDS(800 MHz) or CMOS (250 MHz) levels 

Product Features

Low phase noise phase-locked loop core

Reference input frequencies to 250 MHz

Programmable dual-modulus prescaler

Programmable charge pump (CP) current

Separate CP supply (VCPS) extends tuning range

Two 1.6 GHz, differential clock inputs

8 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

4 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms

4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 275 fs rms

Fine delay adjust on 2 LVDS/CMOS outputs

Serial control port

Space-saving 64-lead LFCSP

Product Applications

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

Product Specification

Product Photos

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