Hot-selling and scarce CYD09S18V18-167BBXC Synchronous SDR Dual Port SRAM BGA spot stock

Product Descriptions

The FullFlex™dual port SRAM families consist of 2-Mbit,4-Mbit,9-Mbit,18-Mbit,and 36-Mbit synchronous,true dual port static RAMs that are high speed,low power 1.8 V or 1.5 V CMOS.Two ports are provided,enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control.For FullFlex72 these ports operate independently with72-bit bus widths and each port is independently configured for two pipelined stages.Each port is also configured to operate in pipelined or flow through mode.

The advanced features include the following:

■ Built in deterministic access control to manage address collisions during simultaneous access to the same memory location

■ Variable Impedance Matching (VIM) to improve data transmission by matching the output driver impedance to the line impedance

■ Echo clocks to improve data transfer

Product Features

■ True dual port memory enables simultaneous access to the shared array from each port

■ Synchronous pipelined operation with single data rate (SDR) operation on each port

❐ SDR interface at 200 MHz

❐ Up to 28.8 Gb/s bandwidth (200 MHz ×72-bit ×2 ports)

■ Selectable pipelined or flow-through mode

■ 1.5 V or 1.8 V core power supply

■ Commercial and Industrial temperature

■ IEEE 1149.1 JTAG boundary scan

■ Available in 484-ball PBGA (×72)and 256-ball FBGA (×36 and ×18)packages

■ FullFlex72 family

❐ 36-Mbit:512 K ×72 (CYD36S72V18)

❐ 18-Mbit:256 K ×72 (CYD18S72V18)

❐ 9-Mbit:128 K ×72 (CYD09S72V18)

❐ 4-Mbit:64 K ×72 (CYD04S72V18)

■ FullFlex36 family

❐ 36-Mbit:1 M ×36 (CYD36S36V18)

❐ 18-Mbit:512 K ×36 (CYD18S36V18)

❐ 9-Mbit:256 K ×36 (CYD09S36V18)

❐ 4-Mbit:128 K ×36 (CYD04S36V18)

❐ 2-Mbit:64 K ×36 (CYD02S36V18)

■ FullFlex18 family

❐ 36-Mbit:2 M ×18 (CYD36S18V18)

❐ 18-Mbit:1 M ×18 (CYD18S18V18)

❐ 9-Mbit:512 K ×18 (CYD09S18V18)

❐ 4-Mbit:256 K ×18 (CYD04S18V18)

■ Built in deterministic access control to manage address collisions

❐ Deterministic flag output upon collision detection

❐ Collision detection on back-to-back clock cycles

❐ First busy address readback

■ Advanced features for improved high speed data transfer and flexibility

❐ Variable impedance matching (VIM)

❐ Echo clocks

❐ Selectable LVTTL (3 .3 V),Extended HSTL (1 .4 V to 1.9 V),1.8 V LVCMOS,or 2.5 V LVCMOS IO on each port

❐ Burst counters for sequential memory access

❐ Mailbox with interrupt flags for message passing

❐ Dual chip enables for easy depth expansion

Product Specifications

Product Photos

For more product information, please download the PDF

WhenCE is HIGH (deselected),the device assumes a standby mode at which the power dissipation can be reduced down to250 µW (typical) with CMOS input levels.