CD54HC4060F3A/5962-8768001EA High-Speed CMOS Logic 14-Stage Binary Counter with Oscillator CDIP16 spot stock

Product Descriptions

The’HC4060 and’HCT4060 each consist of an oscillator section  and  14  ripple-carry  binary  counter  stages.  The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets  the  counter  to  the  all-0’s  state  and  disables  the oscillator.A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of φI (and φO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.

Product Features

•  Onboard Oscillator

•  Common Reset

•  Negative-Edge Clocking

•  Fanout (Over Temperature Range)

-  Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

-  Bus Driver Outputs  . . . . . . . . . . . . . 15 LSTTL Loads

•  Wide Operating Temperature Range      -55oC to 125oC

•  Balanced Propagation Delay and Transition Times

•  Significant Power Reduction Compared to LSTTL Logic ICs

•  HC Types

-  2V to 6V Operation

-  High Noise Immunity: NIL = 30%, NIH = 30% of V CC at V CC = 5V

•  HCT Types

-  4.5V to 5.5V Operation

-  Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max),VIH = 2V (Min)

-  CMOS Input Compatibility, Il≤ 1µA at VOL,VOH

Product Photos

For more product information, please download the PDF

WhenCE is HIGH (deselected),the device assumes a standby mode at which the power dissipation can be reduced down to250 µW (typical) with CMOS input levels.