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Hot-selling and scarce IDTCSP2510DPG 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER TSOP24 spot stock

Manufacturer Product Number
IDTCSP2510DPG
Description

IDTCSP2510DPG 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER TSOP24 spot stock

Package Condition
TaPe & Reel
Datasheet
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Product Descriptions

The CSP2510D is a high performance,low-skew,low-jitter,phase-lockloop (PLL)clock driver.It uses a PLL to precisely align,in both frequencyand phase,the feedback (FBOUT)output to the clock (CLK)input signal .It is specifically designed for use with synchronous DRAMs.The CSP2510Doperates at 3 .3V .

One bank of ten outputs provide low-skew, low-jitter copies of CLK .Output signal duty cycles are adjusted to 50 percent,independent of the dutycycle at CLK .The outputs can be enabled or disabled via the control G input .When the G input is high,the outputs switch in phase and frequency withCLK;when the G input is low,the outputs are disabled to the logic-low state 

Unlike many products containing PLLs,the CSP2510D does not requireexternal RC networks . The loop filter for the PLL is included on-chip,minimizing component count,board space,and cost .

Because  it  is  based on  PLL circuitry, the CSP2510D  requires astabilization time to achieve phase lock of the feedback signal to thereference signal.This stabilization time is required,following power up andapplication of a fixed-frequency, fixed-phase signal at CLK, as well asfollowing any changes to the PLL reference or feedback signals.The PLLcan be bypassed for the test purposes by strapping AVDD to ground .

The CSP2510D is specified for operation from 0°C to +85°C . This deviceis also available (on special order)in Industrial temperature range (-40°Cto +85°C). See ordering information for details .

Product Features

•  Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

•  Distributes one clock input to one bank of ten outputs

•  Output enable bank control

•  External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal

•  No external RC network required for PLL loop stability

•  Operates at 3.3V VDD

•  tpd Phase Error at 166MHz: < ±150ps

•  Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz

•  Spread Spectrum Compatible

•  Operating frequency 50MHz to 175MHz

•  Available in 24-Pin TSSOP package

Product Applications

•  SDRAM Modules

•  PC Motherboards

•  Workstations

Product Photos

IDTCSP2510DPG

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Hot-selling and scarce IDTCSP2510DPG 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER TSOP24 spot stock

IDTCSP2510DPG 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER TSOP24 spot stock

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