Hot-selling and scarce MT46V16M16TG-6T:F DOUBLE DATA RATE DDR SDRAM TSSOP-66 spot stock

Product Descriptions

DDR333 meets or surpasses all DDR266 timing requirements thus assuring full backwards compatibility with current DDR designs. In addition, these devices support concurrent auto-precharge and t RAS lockout for improved timing performance. The 256Mb, DDR333 device will support an (t REFI) average periodic refresh interval of 7.8us.

The standard 66-pin TSOP package is offered for point-to-point applications where the FBGA package is intended for the multi-drop systems.

The Micron 256Mb data sheet provides full specifications and functionality unless specified herein.

Product Features

• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V

• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte)

• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data (x16 has two - one per byte)

• Programmable burst lengths: 2, 4, or 8

• Concurrent Auto Precharge option supported

• Auto Refresh and Self Refresh Modes

• FBGA package available

• 2.5V I/O (SSTL_2 compatible)

• t RAS lockout (tRAP = tRCD)

• Backwards compatible with DDR200 and DDR266

Product Photos

For more product information, please download the PDF